X86 Serializing Instructions

Note that in Intel terminology, 'serializing instruction' has a special meaning: an instruction that flushes the store buffer and the out-of-order instruction pipeline before any later instructions can execute. (They can decode and maybe even issue into the out-of-order core, but not execute).

Compiler options listed by category. 6 minutes to read.In this articleThis article contains a categorical list of compiler options. For an alphabetical list, see. Optimization OptionPurposeCreates small code.Creates fast code.Controls inline expansion.Disables optimization.Deprecated.

Uses global optimizations.Generates intrinsic functions.Favors small code.Favors fast code.A subset of /O2 that doesn't include /GF or /Gy.Omits frame pointer. (x86 only)Produces code that is optimized for a specified architecture, or for a range of architectures.Code generation OptionPurposeUse SSE or SSE2 instructions in code generation.

(x86 only)Produces an output file to run on the common language runtime.Specifies the model of exception handling.Specifies floating-point behavior.Optimizes for Windows applications.Uses the cdecl calling convention. (x86 only)Deprecated. Activates stack probes.Enables string pooling.Calls hook function penter.Calls hook function pexit.Enables whole program optimization.Deprecated. Enables minimal rebuild.Enables run-time type information (RTTI).Uses the fastcall calling convention. (x86 only)Checks buffer security.Controls stack probes.Supports fiber safety for data allocated by using static thread-local storage.Adds control flow guard security checks.Uses the vectorcall calling convention.

(x86 and x64 only)Enables whole-program global data optimization.Deprecated. Enables synchronous exception handling. Use instead.Enables function-level linking.Deprecated.

Enables fast checks. (Same as )Uses the stdcall calling convention. (x86 only)Forces parameters passed in registers to be written to their locations on the stack upon function entry. This compiler option is only for the x64 compilers (native and cross compile).Creates a hotpatchable image.Generates fast transcendentals.Deprecated. Suppresses the call of the helper function ftol when a conversion from a floating-point type to an integral type is required.

Contents.x86 integer instructions This is the full 8086/8088 instruction set of Intel. Most if not all of these instructions are available in 32-bit mode; they just operate on 32-bit registers ( eax, ebx, etc.) and values instead of their 16-bit ( ax, bx, etc.) counterparts. See also for a quick tutorial for this processor family.The updated instruction set is also grouped according to architecture (, ) and more generally is referred to as and (also known as ).Original 8086/8088 instructions Original 8086/8088 instruction setInstructionMeaningNotesOpcodeASCII adjust AL after additionused with unpacked0x37AADASCII adjust AX before division8086/8088 datasheet documents only base 10 version of the AAD instruction ( 0xD5 0x0A), but any other base will work. Later Intel's documentation has the generic form too. If ( DF 0 ). ( word.

) DI =. ( word. ) SI ; else. ( word. ) DI - =. ( word.

) SI -;0xA5MULUnsigned multiply(1) DX:AX = AX. r/m; (2) AX = AL. r/m;0xF6/40xF7/4NEGTwo's complement negationr / m.= - 1;0xF6/30xF7/3No operationopcode equivalent to XCHG EAX, EAX0x90NOTNegate the operand,r / m ^= - 1;0xF6/20xF7/2OR(1) r / m = r / imm; (2) r = m / imm;0x080x0D, 0x800x83/1OUTOutput to port(1) portimm = AL; (2) portDX = AL; (3) portimm = AX; (4) portDX = AX;0xE6, 0xE7, 0xEE, 0xEFPOPPop data fromr/m =.SP; POP CS (opcode 0x0F) works only on 8086/8088. Later CPUs use 0x0F as a prefix for newer instructions.0x07, 0x0F(8086/8088 only), 0x17, 0x1F, 0x580x5F, 0x8F/0POPFPop from stackFLAGS =.SP;0x9DPUSHPush data onto stack.- SP = r / m;0x06, 0x0E, 0x16, 0x1E, 0x500x57, 0x68, 0x6A (both since 80186), 0xFF/6PUSHFPush FLAGS onto stack.- SP = FLAGS;0x9CRCLRotate left (with carry)0xC00xC1/2 (since 80186), 0xD00xD3/2RCRRotate right (with carry)0xC00xC1/3 (since 80186), 0xD00xD3/3REPxxRepeat MOVS/STOS/CMPS/LODS/SCAS( REP, REPE, REPNE, REPNZ, REPZ)0xF2, 0xF3RETReturn from procedureNot a real instruction. Main article:7 new instructions.InstructionDescriptionSHA1RNDS4SHA1NEXTESHA1MSG1SHA1MSG2SHA256RNDS2SHA256MSG1SHA256MSG2Undocumented instructions Undocumented x86 instructions The x86 CPUs contain which are implemented on the chips but not listed in some official documents.

Retrieved 2013-04-21. Toth, Ervin (1998-03-16). Archived from on 1999-11-03. The instruction brings down the upper word of the doubleword register without affecting its upper 16 bits. Coldwin, Gynvael (2009-12-29). Retrieved 2018-10-03.

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Internal (zero-)extending the value of a smaller (16-bit) register applying the bswap to a 32-bit value '00 00 AH AL', truncated to lower 16-bits, which are '00 00'. Bochs bswap reg16 acts just like the bswap reg32 QEMU ignores the 66h prefix. Archived from the original on 2012-03-12.

CS1 maint: BOT: original-url status unknown., section 7.3.2., section 4.3, subsection 'PREFETCHh—Prefetch Data Into Caches'. section 3.5.2.3. Archived from on 2004-11-06. Retrieved 2010-11-07. Archived from on 2003-06-26. Retrieved 2010-11-07.